Static Timing Analysis for Nanometer Designs: A Practical Approach

Description

Static Timing Analysis For Nanometer Designs: A Practical Approach is a panoramic coverage of topics relevant to those who are studying static timing analysis. The book explains the concepts using PrimeTime from Synopsys, Inc. tool. The book is well-complemented with real world examples, timing diagrams and detailed reports. Constraint modelling has been well-illustrated with the modeling language Synopsys Design Constraints. Topics such as delay calculation, cell timing and power modeling, interconnect modeling and analysis, noise, the chip timing verification using static timing analysis and crosstalk have been covered in the book. The topics range from basic to complex nanometer designs, explaining concepts in detail like clock gating, half-cycle paths, on-chip variation and timing of source-synchronous interfaces like DDR.

Timing arcs, interconnect parasitics and coupling, CMOS logic gates, waveform slew, cell library, cell capacitance, timing modeling and pre and post-layout interconnect modelling have also been covered in the book. More concepts on Advanced Modeling and Analysis like power modeling, controlled current source timing and noise models for nanometer technologies, verification of half-cycle and multi-cycle paths, crosstalk timing and crosstalk glitch calculation and false paths are also covered in Static Timing Analysis For Nanometer Designs: A Practical Approach. Appendices in the book include holistic coverage of SPEF, SDC and SDF formats.

The book comes in handy for those who are working in timing verification of ASICs, chip design and also for students specialising in chip design and logic. Overall a good reference book for Static Timing Analysis, it gives a good hands-on experience to understand the basics in depth.

Static Timing Analysis For Nanometer Designs: A Practical Approach was published by Springer in 2009 in hardcover.